1) Field of the Invention
Some example embodiments of the present invention relates to a semiconductor device with lattice-mismatched zone and fabrication method thereof, and more specifically to a strained-channel transistor structure and fabrication method thereof and more particularly to a strained-channel transistor structure and fabrication method comprising a Carbon doped SiGe layer.
2) Description of the Prior Art
Size reduction of the metal-oxide-semiconductor field-effect transistor (MOSFET), including reduction of gate length and gate oxide thickness, has enabled a continuous improvement in speed performance, density, and cost per unit function of integrated circuits during the past few decades.
In order to further enhance performance of the transistor, stress/strain may be introduced in the transistor channel to improve carrier mobility to enhance performance of the transistor in addition to device scaling. There are several existing approaches to introducing strain in a channel region of the transistor.
U.S. Pat. No. 6,844,227: Semiconductor devices and method for manufacturing the same—Inventor: Kubo, Minoru; Mie, Japan
U.S. 20040262694A1: Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel Inventor: Chidambaram, PR
U.S. Pat. No. 6,190,975: Method of forming HCMOS devices with a silicon-germanium-carbon compound semiconductor layer Inventor: Kubo, Minoru; Mie, Japan
U.S. Pat. No. 6,576,535: Carbon doped epitaxial layer for high speed CB-CMOS—Inventor: Drobny, Vladimir F;
U.S. Pat. No. 6,190,975 and U.S. 20020011617A1: semiconductor device and method of producing the same—Inventor: KUBO, MINORU; MIE, Japan
U.S. 20050035369A1: Structure and method of forming integrated circuits utilizing strained channel transistors—Inventor: Lin, Chun-Chieh; Hsin-Chu, Taiwan
However, there is a need to improve upon these methods.